1. Field of the Invention
This invention relates to self-aligned integrated circuits and more particularly to integrated circuits which employ field effect transistors. More specifically, the invention relates to a process for making self-aligned memory cells which form a very high density memory array.
2. Description of the Prior Art
Integrated circuits, particularly those employing field effect transistors formed in a semiconductor substrate, have achieved very high densities of active and passive components. To achieve these high densities various processes have been developed to reduce the size of each circuit and to reduce the area required for isolation within the substrate between the circuits. Furthermore, in order to further increase the densities in the integrated circuits, for example, in the memory technology, very simple circuits have been developed which utilize a very small amount of surface area on the semiconductor substrate. One of the simplest circuits for providing a memory cell is described in commonly owned U.S. Pat. No 3,387,286, filed July 14, 1967, by R. H. Dennard. This cell employes a single field effect transistor as a switch for coupling a capacitor to a bit sense line. In also commonly owned U.S. Pat. Nos. 3,811,076, by W. M. Smith, and 3,841,926, by R. H. Garnache, both filed Jan. 2, 1973, there is disclosed a one device field effect transistor memory cell of the type described in the above identified Dennard patent which utilizes a layer of polycrystalline silicon as a field shield and as an electrode for a storage capacitor in order to improve cell density. To further improve the density of the cells described in U.S. Pat. Nos. 3,811,076 and 3,841,926, the process for making the cells utilizes a dual layer of silicon nitride and silicon dioxide and polysilicon conductive layers or lines.
In U.S. Pat. No. 3,771,147, filed Dec. 4, 1972, there is disclosed a one device field effect transistor memory cell wherein a first level metal, tungsten, is used to provide a self-aligned gate, a single contact at the drain is utilized for two adjacent cells and a metallic layer held at a reference potential serves as an electrode for the storage capacitor.
In U.S. Pat. No. 3,648,125, filed Feb. 2, 1971, there is disclosed a process for making integrated circuits which includes forming electrically isolated pockets by a grid of oxidized silicon extending into silicon material, and in the periodical, Electronics, Sept. 11, 1972, page 31, there is a suggestion that the use of oxide isolation technqiues be employed for making single transistor memory cells.
Electrical isolation techniques wherein a polysilicon grid is used to produce islands of single crystal silicon is disclosed in U.S. Pat. No. 3,736,193, filed July 29, 1969.
Field effect transistors having silicon gates with a nitride-oxide gate dielectric are suggested in U.S. Pat. No. 3,699,646, filed Dec. 28, 1970, and in the periodical, Electronics, dated Aug. 2, 1971, on page 74.
By employing the techniques disclosed in the above identified patents and articles, the semiconductor industry has produced semiconductor circuits or cells which contain thousands of circuits or cells on each small semiconductor substrates or chips, which are generally made of silicon.